The clock-signal generation circuit usually provides repeated signals with a constant period. The repeated signals are used to time the digital synchronized circuit, such as Analog-to-Digital converter (ADC), etc.
Non-overlapping clock-signal is a typical type of clock-signal provided by a clock-signal generation circuit. The non-overlapping clock-signal is normally used in switched-capacitor integrator circuit. The non-overlapping clock-signal is used to generate non-inverted clock-signal and inverted clock-signal. The non-inverted clock-signal and the inverted clock-signal transit between the corresponding delayed non-inverted clock-signal and the delay inverted clock-signal. The transition between the non-inverted clock-signal and the inverted clock-signal also has a delay.
When the non-overlay clock-signal is applied in switched-capacitor integrator used by the high-speed ADC circuit, the non-overlapping time and the clock phase delay are often realized by the invertor delay. In the conventional multiple clock domain non-overlapping clock-signal generation circuit, the non-overlapping time and the clock phase delay are often realized by increasing the invertor time delay of the delay line. However, such approaches may affect the reliability, and increase the power consumption.
The disclosed circuits are directed to solve one or more problems set forth above and other problems in the art.